Aspects are related generally to computer-based communication systems, and more specifically to insertion of data in a multi-source data processing pipeline with an elastic FIFO in a computer system.
Peripheral component interconnect express (PCIe) is a component level interconnect standard that defines a bi-directional communication protocol for transactions between input/output (I/O) adapters and host systems. PCIe communications are encapsulated in packets according to the PCIe standard for transmission on a PCIe bus. Packets originating at I/O adapters and ending at host systems are referred to as upbound packets. Packets originating at host systems and terminating at I/O adapters are referred to as downbound packets. PCIe transactions include a request packet and, if required, a completion packet (also referred to herein as a “response packet”) in the opposite direction. The PCIe topology is based on point-to-point unidirectional links that are paired (e.g., one upbound link, one downbound link) to form the PCIe bus.
PCIe and other communication protocols can use “credits” to limit the rate of requests and ensure that outstanding requests can be serviced before accepting new requests. In a high-bandwidth data pipeline, where there are multiple individual and separately controlled requesters for a destination port, dataflow on main interfaces can be controlled by a credit scheme. A main dataflow path can move gap-less data indefinitely and an “other” source must be able to insert into the data stream within a reasonable time frame. It is desirable to maintain the gap-less data stream before, during, and after insertion. It is also desirable to reduce the main dataflow path latency in the normal case (i.e., no insertion).